There are many advantages to using silicon as a substrate for electronic packaging, rather than traditional ceramic and organic laminate packaging. Some of the key features of the silicon carrier include: the ability to create high performance wiring and joining at much finer pitch than typical packaging, the ability to join heterogeneous technologies or different generation technologies for high speed applications, the ability to integrate passives, MEMS or optical fibers, the ability to add silicon functionality to the carrier package in addition to wiring, the ability to dramatically increase the I/O density, and for many applications, the ability to reduce overall system cost when compared to other system on package (SOP) approaches which do not use Si as the carrier.
Elements and structures of semiconductor packages have been described in U.S. Pat. No. 5,998,292 to Black et al. and U.S. Pat. No. 6,593,644 to Chiu et al. In order to attain the advantages outlined above several key steps are necessary, as shown in FIGS. 1A to 1F. As illustrated in FIG. 1A, first, deep blind vias 10 (several hundred microns in depth) are etched into a silicon wafer 12, and sidewall insulation 14 is deposited. As shown in FIG. 1B, vias 10 must be completely filled with a conductor 16. Once the vias are filled, as shown in FIG. 1C, standard BEOL wiring levels 18 can be built on top of the silicon wafer 12, and the whole wafer can be thinned by backside grinding to expose the via conductors on the backside, as shown in FIG. 1D. As shown in FIG. 1E, solder connections, such as C4 solder balls 20 may then be built on the carrier back, and chips 22 may be joined to the front, by any one of a number of conventional techniques such as flip chip bonding as illustrated in FIG. 1F, completing the high performance silicon carrier package 24.
At this point there are several options, one of which is illustrated in FIG. 2, where the high performance silicon carrier package 24 is joined to a ceramic module 26 by means of solder balls 20, and then to a PC board 28 by means of, for example, additional C4 solder balls 30.
Of all the key technology elements described above, that which is most problematic is the filling of high aspect ratio blind vias with conductor. Filling with common metals by PVD or CVD methods is impractical, while plating becomes extremely difficult due to the tendency for the plated side walls to “breadloaf” at the top, cutting off the via from further filling, and trapping plating solution in a central void. Even if these or other methods of solid metal filling, such as filling with molten metal, could be made to work, typical metals have a large coefficient of thermal expansion (CTE) mismatch with silicon. There are three potential problems associated with large CTE mismatches between the vias and the silicon substrate: delamination at the via side walls; cracking of the silicon substrate between vias; and piston-like rupture of any overlying or underlying structures or thin films in contact with the top/bottom surfaces of the vias. Accordingly it is advantageous to use a material which is simultaneously conductive with a good CTE match to silicon.
One such material which has been used by International Business Machines Corporation in the production of glass ceramic multi-chip modules (MCM) is a paste containing a mixture of copper and glass particles suspended in a mixture of organic solvents and binders. Such pastes are typically applied to a patterned ceramic greensheet by a screen printing method, after which the sheets are stacked and sintered at high temperature, during which the organic components are burned off, and the glass and Cu components coalesce to form conductive lines and vias.
Recently, in “Filling the Via Hole of IC by VPES (Vacuum Printing Encapsulation Systems) for stacked chip (3D packaging)”, Atsushi Okuno and Noriko Fujita, 2002 Electronic Components and Technology Conference have described the adaptation of a vacuum printing encapsulation system (VPES) for filling blind vias with conductive paste. The VPES method was originally used to deliver plastic resin in the manufacture of ball grid array (BGA) and CSP packaging, wafer level CSP packaging, transparent resin encapsulating for light emitting diode (LED) displays, flip-chip under-filling, and other processes. For BGA or CSP packaging, following die bonding and wire bonding on a printed circuit board substrate, the printing of liquid resin takes place using a squeegee applied to the substrate under vacuum. The substrate is then cured at a high temperature to solidify the liquid resin. After curing, solder balls for terminals are mounted on the backside of the substrate. Conventional screen printing lacked a process for removing the gas from the resin after the printed after curing, causing cracking or warping during the high temperature process.
In the method described by Okuno, a squeegee tool applies conductive paste using a knife edge. In this tool design, a vacuum is pulled inside the enclosure, and paste is delivered, for illustrative example, by a slot in the base of the tool.
An example of via filling using such a tool is shown in FIGS. 3A through FIG. 3F. In these figures, a vacuum chamber 34 is evacuated by means of a vacuum pump (not shown) connected to chamber 34 by a vacuum hose 36. Once sufficient vacuum is created, a squeegee blade 38, mounted an a moving member 39, moves across the surface of a via containing wafer 40 from left to right in the figure, held in a wafer holder or base plate 42, delivering paste 44 at its leading edge. Paste 44 is moved into position by a moving support 46 in a channel or base plate slot 48 to which paste 44 is conducted by a passageway (not shown). As shown in FIG. 3C, excess paste is deposited over a movable support member 50 in a channel or base plate slot 52. As shown in FIG. 3D, support member 52 is moved upwards in channel 52, while support member 46 is moved downwards in channel 48. Additional paste is supplied to slot 52 through a second passageway (not shown). As illustrated in FIG. 3E and FIG. 3F, moving member 39 is then moved to cause squeegee blade 38 to again traverse wafer 40, while moving from right to left in the figure.
This method has a number of important shortcomings, the most important of which is that there is not sufficient constraint at the leading edge of the squeegee blade 38 to force the paste 44 to the bottom of a deep blind via in a single, or often, even multiple passes. Whether the paste 44 makes it to the via bottom is dependent on a number of factors including the viscosity of the paste 44, the down force on the squeegee blade 38, the quantity of paste 44 built up in front of the squeegee blade 38, and the blade speed. With respect to the down force, there is no method to fully contain the paste 44 under pressure over a blind via except when the squeegee blade 38 is passing directly overhead, and even then paste 44 is free to smear out both in front of and behind the blade 38. This makes multiple passes a necessity. For high aspect ratio vias incomplete filling can occur if the vacuum level is not sufficiently low or if the paste 44 is of a very high viscosity. The method is also not well suited to semiconductor processing where substrates are round rather than rectangular. In order to ensure complete coverage of a round substrate, paste 44 must be pushed repeatedly onto and off of the base plate 42 holding the wafer. The linear motion of the squeegee blade 38 then leads to buildup at either end of the tool necessitating some method of regular cleaning, and a great waste of the conductive fill paste. Accordingly there is a need to develop a more efficient method for applying viscous conductive paste to semiconductor wafers containing blind vias.
In U.S. Pat. No. 5,244,143 to Ference et al. as well as U.S. Pat. No. 5,775,569 to Berger et al., a tool and method for filling a mold with molten solder are described. Since a mold is obviously a rigid plate containing etched regions of specific shapes, if these shapes take the form of cylinders then the problem is essentially one of filling blind vias. The filling head described in these patents is sealed against the mold surface such that a vacuum can be pulled in a region defined by a O-ring seal underneath the head. Molten solder is then delivered through a central slot in the head such that complete fill of the evacuated solder mold cavities is achieved in a single pass. An important distinguishing feature of this tool and method is that it works well only for very low viscosity materials such as molten solder which have a viscosity on the order of 2 centipoise (for comparison water is by definition 1 centipoise). The conductive pastes used for semiconductor applications by contrast have much higher viscosities ranging from 1,000 centipoise to greater than 50,000 centipoise and thus require much higher internal pressures for them to be effectively delivered to the wafer surface and into the blind vias etched therein.
A via filling method using a pressurized paste nozzle is described in U.S. Pat. No. 6,506,332 to J. L. Pedigo and it is clear that while this method has advantages over the squeegee method described by Okuno, it is primarily intended for use in organic printed circuit board (PCB) high-density interconnect (HDI) and sequential build up (SBU) laminate board type applications. The apparatus described makes use of a pressure head in combination comprising an O-ring gasket which is held against the electronic substrate to be filled and moved relative to that substrate such that paste is forced into the via holes as the head passes overhead. The apparatus as described has a number of shortcomings which limit its applicability for use with silicon wafer based packaging. Specifically, the method does not employ vacuum which is a practical necessity for complete filling of small, high aspect ratio blind vias. Instead, the method is described as a means of obtaining “reduced numbers of air pockets formed in the via fill paste while decreasing the amount of processing required per board”. Further, via sizes claimed range from 2 to 25 thousands of an inch (mils) in diameter, a span which covers most important electronic wiring board applications, but which neglects via features smaller than 50 um (2 mils) in diameter which are easily attainable in package substrates made from silicon where blind vias may be on the order of 10 um in diameter with aspect ratios greater than 10:1. Filling such small blind features with viscous paste without the aid of vacuum is highly problematic if not impossible.